A semiconductor memory module typically comprises a printed circuit board and a plurality of semiconductor memory components mounted thereon. The semiconductor memory module may furthermore comprise a control component, for example a HUB chip, and also a bus system, the control component controlling read and write access to the semiconductor memory components by means of control signals transmitted via the bus system.
In order to increase the storage density of the semiconductor memory module, the semiconductor memory components preferably comprise a plurality of semiconductor memory devices arranged in housings stacked one above another.
FIG. 1 shows a cross-sectional view of a semiconductor memory component 2 comprising a first 50 and a second 60 semiconductor memory device, the second semiconductor memory device 60 being arranged on the first semiconductor memory device 50. Each of the semiconductor memory devices 50 and 60 has a housing 55 and 65 and an underside 56 and 66. Each of the housings 55 and 65 has a top side 58 and 68. Situated in the housing 55 and 65 is an integrated semiconductor memory chip 52 and 62 mounted on a printed circuit board (not shown in FIG. 1). A plurality of semiconductor memory chips 52 and 62 may also be arranged one above another in each of the housings 55 and 65.
Each of the semiconductor memory devices 50 and 60 has, at the underside 56 and 66, connection contacts 53 and 63 connected to the semiconductor memory chips 52 and 62 via bonding wires (not shown in FIG. 1) arranged in a potting compound 54 and 64. Each of the connection contacts 53 and 63 of the semiconductor memory devices 50 and 60 is connected to respective external contacts 51 and 61 of the semiconductor memory devices 50 and 60. The external contacts 51 and 61 of the semiconductor memory devices 50 and 60 are preferably formed as solder balls. A filler material 57 and 67 is provided between the individual external contacts 51 and 61.
The external contacts 51 and 61 of the semiconductor memory devices 50 and 60 are in each case organized in groups of first external contacts 51a and 61a and second external contacts 51b and 61b of the semiconductor memory devices 50 and 60. The first external contacts 51a and 61a of the semiconductor memory devices 50 and 60 are arranged on respective first sections of the semiconductor memory devices 50 and 60 as a matrix in the vicinity of first lateral ends 59a and 69a of the semiconductor memory devices 50 and 60. The second external contacts 51b and 61b of the semiconductor memory devices 50 and 60 are arranged on respective second sections of the semiconductor memory devices 50 and 60 as a matrix in the vicinity of second lateral ends 59b and 69b of the semiconductor memory devices 50 and 60. In the present cross-sectional view, each matrix comprises three columns and, by way of example, eleven rows (not shown in FIG. 1).
The first external contacts 61a of the second semiconductor memory device 60 are connected to first contacts 70a of the semiconductor memory component 2 via electrically conductive conductor tracks 81a. The electrically conductive conductor tracks 81a are arranged on a surface of a first flexible substrate 82a. 
A first end section of the first flexible substrate 82a is arranged between the top side 58 of the first section of the first semiconductor memory device 50 and the underside 66 of the first section of the second semiconductor memory device 60. The first end section of the first flexible substrate 82a is fixed at the top side 58 of the first semiconductor memory device 50 by means of a first adhesion agent 80a. 
A second end section of the first flexible substrate 82a is arranged between the first external contacts 51a of the first semiconductor memory device 50 and the first contacts 70a of the semiconductor memory component 2.
The second external contacts 61b of the second semiconductor memory device 60 are connected to second contacts 70b of the semiconductor memory component 2 via electrically conductive conductor tracks 81b. The electrically conductive conductor tracks 81b are arranged on a surface of a second flexible substrate 82b. 
A first end section of the second flexible substrate 82b is arranged between the top side 58 of the second section of the first semiconductor memory device 50 and the underside 66 of the second section of the second semiconductor memory device 60. The end section of the second flexible substrate 82b is fixed at the top side 58 of the first semiconductor memory device 50 by means of a second adhesion agent 80b. 
A second end section of the second flexible substrate 82b is arranged between the second external contacts 51b of the first semiconductor memory device 50 and the second contacts 70b of the semiconductor memory component 2.
An electrically conductive connection between the first external contacts 61a of the second semiconductor memory device 60 and the first contacts 70a of the semiconductor memory component 2 is provided via the electrically conductive conductor track 81a arranged in the first flexible substrate 82a. 
An electrically conductive connection between the second external contacts 61b of the second semiconductor memory device 60 and the second contacts 70b of the semiconductor memory component 2 is provided via the electrically conductive conductor track 81b arranged in the second flexible substrate 82b. 
By contrast, the first 51a and second 51b external contacts of the first semiconductor memory device 50 are connected almost directly to the respective first 70a and second contacts 70b of the semiconductor memory component 2 via plated-through holes through the flexible substrates 82a and 82b. 
The first contacts 70a of the semiconductor memory component 2 serve as input contacts of the semiconductor memory component 2 in order to receive signals from the control component (not shown in FIG. 1). The signals are transmitted to the respective first external contacts 51a and 61a of the first 50 and second 60 semiconductor memory devices via the respective electrically conductive connections. The second contacts 70b of the semiconductor component 2 serve as output contacts of the semiconductor component 2 in order to transmit signals proceeding from the second external contacts 51b and 61b from the first 50 and, respectively, the second 60, semiconductor memory device to the control component (not shown in FIG. 1).
In the case of this arrangement, data signals, proceeding from the control component, run via the first contacts 70a of the semiconductor memory component 2 in parallel through the first 50 and the second 60 semiconductor memory device before they are transmitted to the control component via the second contacts 70b of the semiconductor memory component 2.
On account of the different length of the connection between the control component and the first semiconductor memory device 50 and the connection between the control component and the second semiconductor memory device 60, signal propagation time differences arise.
Therefore, there is a need to provide an improved arrangement of semiconductor memory devices
Furthermore, there is a need to provide an improved semiconductor memory module in which the signal quality of a data transmission between a control component and a memory component is improved.